Counterfeit materials and refurbished materials frequently occur in the electronic component supply chain, so what are the chip detection methods? How to do chip testing?
What are the chip detection methods？
The methods of chip functional testing include board-level test, wafer CP test, packaged FT test, system-level SLT test, reliability test, multiple strategies.
Board-level test: mainly used in functional testing, using the PCB board combined with the chip to build a 'simulated' chip working environment, extracting the chip's interface, testing the function of the chip, or viewing the chip in various harsh environments can work normally. The equipment that needs to be applied is mainly instrumentation, and the main thing that needs to be made is the EVB evaluation board.
System-level SLT testing: is often used in functional testing, performance testing and reliability testing, and often exists as a supplement to finished FT testing. Run the function in the environment to detect its quality, the disadvantage is that it can only cover a part of the function, and the coverage rate is low, so it is generally a supplementary means of FT.
Reliability test: is mainly to apply various harsh environments to the chip, such as ESD static electricity, which is to simulate the human body or simulate an industrial body to apply an instantaneous large voltage to the chip.
Packaged FT test: of finished products after packaging, often used in functional testing, performance testing and reliability testing, to check whether the chip function is normal, and whether there are defects in the packaging process, and help the chips used in reliability testing. , After the fire, snow and thunder and lightning, is it still working?
Wafer CP test: often used in functional test and performance test, to know whether the chip function is normal, and to screen out faulty chips in the chip wafer.
Multiple strategies
How to do chip testing?
1.Test Machine
The tester is a special device for testing the function and performance of the chip. During the test, the tester applies an input signal to the chip to be tested, and the obtained output signal is compared with the expected value to judge the electrical performance of the chip and the effectiveness of the product function.
In the CP and FT testing links, the testing machine transmits the results to the probe station and the sorter respectively. When the probe station receives the test results, an inkjet operation is performed to mark defective chips on the wafer; when the sorter receives the results from the tester, the chips are selected and sorted.
2.Probe machine
The probe station is used for the CP test link after wafer processing and before the packaging process. It is responsible for the transportation and positioning of the wafer, so that the dies on the wafer are sequentially contacted with the probe and tested one by one. The workflow of the probe station is:
1. Move the wafer under the wafer camera through the stage
2. Take the wafer image through the wafer camera to determine the wafer position
3. Move the probe camera under the probe card to determine the position of the probe head
4. Move the wafer under the probe card
5. The needle alignment is realized by the vertical movement of the slide table.
3.Sorting machine
The sorting machine is used in the FT test link after chip packaging. It is a back-end test equipment that provides chip screening and classification functions. The sorting machine is responsible for transporting the input chips to the test module according to the pick-and-place method designed by the system to complete the circuit pressure test. In this step, the sorting machine selects and classifies the circuits according to the test results.
As the core component of electronic products, the performance of the chip is becoming more and more perfect. In order to ensure the quality of the chip, people have adopted effective testing technology to test the function of the chip. Wafer confirmation, as the complexity of the design increases, the workload and the difficulty of the operation increase by orders of magnitude. Verifiers run complex simulations on design engineering, describe chip product specifications into various functions in the form of binary waveforms, process complex state spaces, and detect errors. These are the biggest challenges facing verification engineers.
Perceptive not only is the most professional company in the stock supply of discontinued and scarce materials, but also provide QC inspection for your electronic components.
The following are the inspection items we can provide, if necessary, please contact us at Sales@perceptive-ic.com.
External Visual Inspection: Condition Observed checking Remarking and Re-surfacing
Solvent Test for Re-Surfacing - Dynasolve
Internal Construction / Lead Frame / Wire Bond / Die layout
Electrical Test (MIL-STD-883 or Manufacturer Specifications)
Solderability Verification
Decapsulation Internal Analysis
Die Verification
