1. Standards for automotive semiconductor devices
AEC is actually the abbreviation of Automotive Electronics Council, and the AECQ standard includes the following areas. For electronic devices in different fields, different standards are applicable. At present, the most common ones are AEC-Q100, AEC-Q101, and AEC-Q200.
Standard category | Applicable fields |
AEC-Q100 | Integrated Circuit IC |
AEC-Q101 | Discrete device |
AEC-Q102 | Discrete Photoelectric LEDs |
AEC-Q103 | sensor |
AEC-Q10 4 | Multichip Components |
AEC-Q200 | passive device |
2. Substandards of AEC-Q100
Similar to the DV test of general auto parts, the AECQ standard is actually a test standard that recognizes the design of the chip itself. It is divided into different test sequences to test the chip in different dimensions.
Since the hottest chips are currently the focus of the country and even the world, let's take a look at the test standards for chips first. AEC-Q100 is divided into 13 sub-standards, namely AEC-Q100 main standard and 12 sub-standards from 001 to 012.
standard encdoing | standard name |
AEC-Q100 Rev-H | Failure Mechanism Based Stress Test Qualification For Integrated Circuits(base document |
AEC-Q100-001 | Wire Bond Shear Test |
AEC-Q100-002 | Human Body Model (HBM) Electrostatic Discharge Test |
AEC-Q100-003 | Machine Model (MM) Electrostatic Discharge Test |
AEC-Q100-004 | IC Latch-Up Test |
AEC-Q100-005 | Non-Volatile Memory Program/Erase Endurance, Data Retention, and Operational Life Test |
AEC-Q100-006 | Electro-Thermally Induced Parasitic Gate Leakage Test (GL) |
AEC-Q100-007 | Fault Simulation and Test Grading |
AEC-Q100-008 | Early Life Failure Rate (ELFR) |
AEC-Q100-009 | Electrical Distribution Assessment |
AEC-Q100-010 | Solder Ball Shear Test |
Test sequence A | Accelerated Environment Stress |
Test sequence B | Accelerated Lifetime Simulation |
Test sequence C | Package Assembly Integrity |
Test sequence D | Die Fabrication Reliability |
Test sequence E | Electrical Verification |
Test sequence F | Defect Screening |
Test sequence G | Cavity Package Integrity |
Like the sequence and classification of the DV test, the chip test certification includes a total of 7 sequences, as follows, and the tests of these seven sequences also refer to those test methods defined in AEC-Q100.
The test of the chip also has a certain test sequence, which is also defined in the AEC-Q100 standard. There are a total of 7 test sequences, which add up to 42 test items according to the two levels. These test items are not suitable for all ICs. It is necessary to test the adaptability according to the type of IC, and also need to test according to the temperature level of the chip. Modification of conditions.
The test temperature is also known as the Grade level. In the automotive chip, it is divided into 4 temperature levels, as follows:
Grade | Ambient Operating Temperature Range |
0 | -40 °C to + 150 °C |
1 | -40 °C to + 125 °C |
2 | -40 °C to + 105 °C |
3 | -40 °C to + 85 °C |
The detailed test items in each test sequence are also described in detail in the AEC-Q100 standard, and the test time of each test is also given different requirements according to the Grade level. In the test of AEC-Q100, for sequence A, the number of samples tested is 77, and 0 Fails is required, which greatly increases the confidence of the chip test.
TEST GROUP A – ACCELERATED ENVIRONMENT STRESS TESTS | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
A1 | Preconditioning | PC | 77 |
A2 | Temperature Humidity-Bias or Biased HAST | THB or HAST | 77 |
A3 | Autoclave or Unbiased HAST or Temperature Humidity (without Bias) | AC or UHST or TH | 77 |
A4 | Temperature Cycling | TC | 77 |
A5 | Power Temperature Cycling | PTC | 45 |
A6 | High Temperature Storage Life | HTSL | 45 |
TEST GROUP B – ACCELERATED LIFET | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
B1 | High Temperature Operating Life | HTOL | 77 |
B2 | Early Life Failure Rate | ELFR | 800 |
B3 | NVM Endurance, Data Retention, and Operational Life | EDR | 77 |
TEST GROUP C – PACKAGE ASSEMBLY INTEGRITY TESTS | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
C1 | Wire Bond Shear | WBS | 30 bonds from a minimum of 5 devices |
C2 | Wire Bond Pull | WBP | |
C3 | Solderability | SD | 15 |
C4 | Physical Dimensions | PD | 10 |
C5 | Solder Ball Shear | SBS | 5 balls from a min. of 10 devices |
C6 | Lead Integrity | LI | from each 10 leads |
TEST GROUP D – DIE FABRICATION RELIABILITY TESTS | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
D1 | Electromigration | EM | --- |
D2 | Time Dependent Dielectric Breakdown | TDDB | --- |
D3 | Hot Carrier Injection | HCI | --- |
D4 | Negative Bias Temperature Instability | NBTI | --- |
D5 | Stress Migration | SM | --- |
TEST GROUP E – ELECTRICAL VERIFICATION TESTS | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
E1 | Pre- and Post-Stress Function/Parameter | TEST | All |
E2 | Electrostatic Discharge Human Body Model | HBM | See Test Method |
E3 | Electrostatic Discharge Charged Device Model | CDM | See Test Method |
TEST GROUP E – ELECTRICAL VERIFICATION TESTS (CONTINUED) | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
E4 | Latch-Up | LU | 6 |
E5 | Electrical Distributions | ED | 30 |
E6 | Fault Grading | FG | --- |
E7 | Characterization | CHAR | --- |
E9 | Electromagnetic Compatibility | EMC | 1 |
E10 | Short Circuit Characterization | SC | 10 |
E11 | Soft Error Rate | SER | 3 |
E12 | Lead (Pb) Free | LF | See Test Method |
TEST GROUP F – DEFECT SCREENING TESTS | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
F1 | Process Average Testing | PAT | --- |
F2 | Statistical Bin/Yield Analysis | SBA | --- |
TEST GROUP G – CAVITY PACKAGE INTEGRITY TESTS | |||
# | STRESS | ABV | SAMPLE SIZE / LOT |
G1 | Mechanical Shock | MS | 15 |
G2 | Variable Frequency Vibration | VFV | 15 |
G3 | Constant Acceleration | CA | 15 |
G4 | Gross/Fine Leak | GFL | 15 |
G5 | Package Drop | DROP | 5 |
G6 | Lid Torque | LT | 5 |
G7 | Die Shear | DS | 5 |
G8 | Internal Water Vapor | IWV | 5 |
